Input Ladder logic program Outputs L1 L2 OFF I:1/3 I:1/3 O:2/5 Force> ON O:2/5 O:2/6 O:2/5 O:2/6 M DN_PL Diagrams, such as this one illustrating an overview of the function xiv I/O Module DeviceNet Conventional system Scanner Module DeviceNet system 4-wire cable and connector Coverage of communications and control networks utilizes clear graphics to demonstrate how things work BULLETED LISTS break down processes to helpfully summarize execution of tasks DN Ladder logic EN_PL Figure 15-110 Comparison between ladder logic and the FBD equivalent for a 10 second TON and TONR timer. • When the Motor_Stop button is opened the output of the BAND block turns false to de-energize the contactor coil and stop the motor. Figure 15-110 shows a comparison between ladder logic and the FBD equivalent for the 10 second TON (ondelay timer) and TONR (on-delay with reset). The operation of the FBD can be summarized as follows: • When the Timer_Sw is closed, the TONR function block timer turns true and starts accumulating time. • The accumulated time is monitored by the output reference tag named ACC. • The EN (enable bit) output changes to 1 to turn on the EN_PL. • The TT (timer timing bit) output changes to 1 to turn on the TT_PL. • The timer times out after 10 seconds to set the DN (done bit) to 1 and turn on the DN_PL and reset the TT bit to zero and turn off the TT_PL. • The EN bit and EN_PL remain on as long as the Timer_Sw stays toggled closed. • Opening the Timer_Sw resets all outputs as well as the accumulated value to zero. • The timer can also be reset by way of the Reset input. Figure 15-111 shows a comparison between ladder logic and the FBD equivalent for the Up/Down counter used to limit the number of parts stored in a buffer zone to 50. The operation of the FBD can be summarized as follows: • The CTUD up/down counter function block accumulated value is initially reset by momentary actuation of the Restart_Button. • The accumulated count is monitored by the output reference tag named ACC. • Each time a part enters the buffer zone, the Enter_ Limit_Sw is actuated and the CUEnable input turns true to increment the count by 1. • Each time a part exits the buffer zone, the Exit_ Limit_Sw is actuated and the CDEnable input turns true to decrement the count by 1. • Whenever the number of parts in the buffer zone reaches 50 the DN bit is set to 1 and the output of 10000 0 DN_PL 0 TT_PL 0 EN_PL Status_Timer.DN DN_PL <Local:2:O.Data.3> Status_Timer.TT Input L1 TT_PL <Local:2:O.Data.2> Status_Timer.EN Timer On Delay EN Timer Status_Timer Preset 10000 Accum 0 EN_PL <Local:2:O.Data.1> Timer_Sw <Local:1:I.Data.6> TON FBD equivalent TONR_01 TONR ... Timer On Delay with Reset TimerEnable ACC PRE Reset EN TT DN Timer_Sw Outputs L2 TT_PL 0 ACC_Value 0 10000 Timer_Sw block programming language, help students put the pieces together Operation of the program can be viewed in real time Wash_In_Use Wash_In_Use L Wash_In_Use U Motor_Stop <Local:1:I.Data.0> Motor_Start <Local:1:I.Data.1> Track_Motor <Local:2:O.Data.0> Discrete I/O Slot 1 00 01 02 03 Slot 2 00 01 02 03 Exit_LS <Local:1:I.Data.3> Enter_LS <Local:1:I.Data.2> Do_Not_Enter_Sign <Local:2:O.Data.1> Track_Motor <Local:2:O.Data.0> More than 175 SLC-500 and ControlLogix program simulation videos tied directly to the programs studied in the text • The processor ignores the actual state of input limit switch I:1/3. • Although limit switch I:1/3 is o (0 or false) the processor considers it as being in the on (1 or true) state. • The program scan records this, and the program is executed with this forced status. • In other words, the program is executed as if the limit switch were actually closed. ON ON
Petruzella_ProgrammableLogicControllers__5e
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