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electrical continuity), the corresponding bit in the input image table will be set to a 1. In a rung of any hardwired circuit there must be electrical continuity in order for the load to energize. The rung has electrical continuity only when the current flow is established in a path from one side of the power rail to the other. There is no electrical continuity in the PLC ladder logic program. Instead, the rung must be evaluated in terms of logical continuity rather than electrical continuity. When there is a continuous path of true conditional instructions in a rung, logical continuity exists; accordingly the output instruction is true and the status bit will be set to a 1 (ON). The controller evaluates ladder logic rung instructions based on the rung condition preceding the instruction (rung-condition-in), as illustrated in Figure 5-10. • If the rung-condition-in to an input instruction is true, the controller evaluates the instruction and sets the rung-condition-out to match the results of the evaluation. • If the instruction evaluates to true, the rungcondition out is true. • If the instruction evaluates to false, the rungcondition out is false. • If the rung-condition-in to an output instruction is true, the rung-condition-out is set to true. • If the rung-condition-in to an output instruction is false, the rung-condition-out is set to false. Figure  5-11 illustrates the scan process applied to a simple single rung program. The operation of the scan process can be summarized as follows: • If the input device connected to address I:3/6 is closed, the input module circuitry senses voltage at the input terminal and a 1 (ON) condition is entered into the input image table bit I:3/6. • During the program scan, the processor examines bit I:3/6 for a 1 (ON) condition. • In this case, because input I:3/6 is 1, the rung is said to be TRUE or have logic continuity. single scan can vary from about 1 to 20 ms. If a controller has to react to an input signal that changes states twice during the scan time, it is possible that the PLC will never be able to detect this change. For example, if it takes 8 ms for the CPU to scan a program, and an input contact is opening and closing every 4 ms, the program may not respond to the contact changing state. The CPU will detect a change if it occurs during the update of the input image table file, but the CPU will not respond to every change. The scan time is a function of the following: • The speed of the processor module • The length of the ladder program • The type of instructions executed • The actual ladder true/false conditions The actual scan time is calculated and stored in the PLC’s memory. The PLC computes the scan time each time the END instruction is executed. Scan time data can be monitored via the PLC programming. Typical scan time data include the maximum scan time and the last scan time. The scan is normally a continuous and sequential process of reading the status of inputs, evaluating the control logic, and updating the outputs. Figure 5-9 shows an overview of the data flow during the scan process. For each rung executed, the PLC processor will: • Examine the status of the input image table bits. • Solve the ladder logic in order to determine logical continuity. • Update the appropriate output image table bits, if necessary. • Copy the output image table status to all of the output terminals. Power is applied to the output device if the output image table bit has been previously set to a 1. • Copy the status of all of the input terminals to the input image table. If an input is active (i.e., there is Input modules Input data Output data Input image table file Output image table file Return result Output modules Take some action Examine data Program Check/compare/examine specific conditions Figure 5-9  Overview of the data flow during the scan process. Input instructions L1 L2 S1 Rung-in condition Rung-out condition Output instructions PL1 PL1 PL2 S2 PL2 S1 S2 Figure 5-10  Evaluating ladder logic rung conditions. Basics of PLC Programming  Chapter 5 79


Petruzella_ProgrammableLogicControllers__5e
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