TABLE OF CONTENTS

PREFACE

CHAPTER 1 DESIGN CONCEPTS

1.1 DIGITAL HARDWARE

1.1.1 Standard Chips

1.1.2 Programmable Logic Devices

1.1.3 Custom-Designed Chips

1.2 THE DESIGN PROCESS

1.3 DESIGN OF DIGITAL HARDWARE

1.3.1 Basic Design Loop

1.3.2 Design of a Digital Hardware Unit

1.4 LOGIC CIRCUIT DESIGN IN THIS BOOK

1.5 THEORY AND PRACTICE

1.6 REFERENCES

CHAPTER 2 INTRODUCTION TO LOGIC CIRCUITS

2.1 VARIABLES AND FUNCTIONS

2.2 INVERSION

2.3 TRUTH TABLES

2.4 LOGIC GATES AND NETWORKS

2.4.1 Analysis of a Logic Network

2.5 BOOLEAN ALGEBRA

2.5.1 The Venn Diagram

2.5.2 Notation and Terminology

2.5.3 Precedence of Operations

2.6 SYNTHESIS USING AND, OR AND NOT GATES

2.6.1 Sum-of-Products and Product-of-Sums Forms

2.7 DESIGN EXAMPLES

2.7.1 Three-way Light Control

2.7.2 Multiplexer Circuit

2.8 INTRODUCTION TO CAD TOOLS

2.8.1 Design Entry

2.8.2 Synthesis

2.8.3 Functional Simulation

2.8.4 Summary

2.9 INTRODUCTION TO VHDL

2.9.1 Representation of Digital Signals in VHDL

2.9.2 Writing Simple VHDL Code

2.9.3 How NOT to Write VHDL Code

2.10 CONCLUDING REMARKS

2.11 PROBLEMS

2.12 REFERENCES

CHAPTER 3 IMPLEMENTATION TECHNOLOGY

3.1 TRANSISTOR SWITCHES

3.2 NMOS LOGIC GATES

3.3 CMOS LOGIC GATES

3.3.1 Speed of Logic Gate Circuits

3.4 NEGATIVE LOGIC SYSTEM

3.5 STANDARD CHIPS

3.5.1 7400-series Standard Chips

3.6 PROGRAMMABLE LOGIC DEVICES

3.6.1 Programmable Logic Array (PLA)

3.6.2 Programmable Array Logic (PAL)

3.6.3 Programming of PLAs and PALs

3.6.4 Complex Programmable Logic Devices (CPLDs)

3.6.5 Field-Programmable Gate Arrays

3.6.6 Using CAD Tools to Implement Circuits in CPLDs and FPGAs

3.7 CUSTOM CHIPS, STANDARD CELLS AND GATE ARRAYS

3.8 PRACTICAL ASPECTS

3.8.1 MOSFET Fabrication and Behavior

3.8.2 MOSFET On-Resistance

3.8.3 Voltage Levels in Logic Gates

3.8.4 Noise Margin

3.8.5 Dynamic Operation of Logic Gates

3.8.6 Power Dissipation in Logic Gates

3.8.7 Passing 1s and 0s Through Transistor Switches

3.8.8 Fan-in and Fan-out in Logic Gates

3.9 TRANSMISSION GATES

3.9.1 Exclusive-OR Gates

3.9.2 Multiplexer Circuit

3.10 IMPLEMENTATION DETAILS FOR SPLDS, CPLDS, and FPGAs

3.10.1 Implementation in FPGAs

3.11 CONCLUDING REMARKS

3.12 PROBLEMS

3.13 REFERENCES

CHAPTER 4 OPTIMIZED IMPLEMENTATION OF LOGIC
FUNCTIONS

4.1 KARNAUGH MAP

4.2 STRATEGY FOR MINIMIZATION

4.2.1 Terminology

4.2.2 Minimization Procedure

4.3 MINIMIZATION OF PRODUCT-OF-SUMS FORMS

4.4 INCOMPLETELY SPECIFIED FUNCTIONS

4.5 MULTIPLE-OUTPUT CIRCUITS

4.6 NAND AND NOR LOGIC NETWORKS

4.7 MULTI-LEVEL SYNTHESIS

4.7.1 Factoring

4.7.2 Functional Decomposition

4.7.3 Multi-Level NAND and NOR Circuits

4.8 ANALYSIS OF MULTI-LEVEL CIRCUITS

4.9 CUBICAL REPRESENTATION

4.9.1 Cubes and Hypercubes

4.9.2 Two-dimensional Cube

4.10 MINIMIZATION USING CUBICAL REPRESENTATION

4.10.1 Generation of Prime Implicants

4.10.2 Determination of Essential Prime Implicants

4.10.3 Complete Procedure For Finding a Minimal Cover

4.11 PRACTICAL CONSIDERATIONS

4.12 CAD TOOLS

4.12.1 Logic Synthesis and Optimization

4.12.2 Physical Design

4.12.3 Timing Simulation

4.12.4 Summary of Design Flow

4.12.5 Examples of Circuits Synthesized From VHDL Code

4.13 CONCLUDING REMARKS

4.14 PROBLEMS

4.15 REFERENCES

CHAPTER 5 NUMBER REPRESENTATION AND ARITHMETIC
CIRCUITS

5.1 POSITIONAL NUMBER REPRESENTATION

5.1.1 Unsigned Integers

5.1.2 Conversion Between Decimal and Binary Systems

5.1.3 Octal and Hexadecimal Representations

5.2 ADDITION OF UNSIGNED NUMBERS

5.2.1 Decomposed Full-Adder

5.2.2 Ripple-Carry Adder

5.2.3 Design Example

5.3 SIGNED NUMBERS

5.3.1 Negative Numbers

5.3.2 Addition and Subtraction

5.3.3 Adder and Subtractor Unit

5.3.4 Radix-Complement Schemes

5.3.5 Arithmetic Overflow

5.3.6 Performance Issues

5.4 FAST ADDERS

5.4.1 Carry-Lookahead Adder

5.5 DESIGN OF ARITHMETIC CIRCUITS USING CAD TOOLS

5.5.1 Design of Arithmetic Circuits using Schematic Capture

5.5.2 Design of Arithmetic Circuits using VHDL

5.5.3 Representation of Numbers in VHDL Code

5.5.4 Arithmetic Assignment Statements

5.6 MULTIPLICATION

5.6.1 Array Multiplier for Unsigned Numbers

5.6.2 Multiplication of Signed Numbers

5.7 OTHER NUMBER REPRESENTATIONS

5.7.1 Fixed-Point Numbers

5.7.2 Floating-Point Numbers

5.7.3 Binary-Coded-Decimal Representation

5.8 ASCII Character Code

5.9 PROBLEMS

5.10 REFERENCES

CHAPTER 6 COMBINATIONAL CIRCUIT BUILDING BLOCKS

6.1 MULTIPLEXERS

6.1.1 Synthesis of Logic Functions Using Multiplexers

6.1.2 Multiplexer Synthesis Using Shannon's Expansion

6.2 DECODERS

6.2.1 Demultiplexers

6.3 ENCODERS

6.3.1 Binary Encoders

6.3.2 Priority Encoders

6.4 CODE CONVERTERS

6.5 ARITHMETIC COMPARISON CIRCUITS

6.6 VHDL FOR COMBINATIONAL CIRCUITS

6.6.1 Assignment Statements

6.6.2 Selected Signal Assignment

6.6.3 Conditional Signal Assignment

6.6.4 Generate Statements

6.6.5 Concurrent and Sequential Assignment Statements

6.6.6 Process Statement

6.6.7 Case Statement

6.7 Summary

6.8 PROBLEMS

6.9 REFERENCES

 

CHAPTER 7 FLIP-FLOPS, REGISTERS AND COUNTERS, AND A SIMPLE

PROCESSOR

7.1 BASIC LATCH

7.2 GATED SR LATCH

7.2.1 Gated SR Latch with NAND Gates

7.3 GATED D LATCH

7.3.1 Effects of Propagation Delays

7.4 MASTER-SLAVE AND EDGE-TRIGGERED D FLIP-FLOPS

7.4.1 Master-Slave D Flip-Flop

7.4.2 Edge-Triggered D Flip-flop

7.4.3 D Flip-Flops with Clear and Preset

7.5 T FLIP-FLOP

7.5.1 Configurable Flip-flops

7.6 JK FLIP-FLOP

7.7 SUMMARY OF TERMINOLOGY

7.8 REGISTERS

7.8.1 Shift Register

7.8.2 Parallel-Access Shift Register

7.9 COUNTERS

7.9.1 Asynchronous Counters

7.9.2 Synchronous Counters

7.9.3 Counters with Parallel Load

7.10 RESET SYNCHRONIZATION

7.11 OTHER TYPES OF COUNTERS

7.11.1 BCD Counter

7.11.2 Ring Counter

7.11.3 Johnson Counter

7.11.4 Remarks on Counter Design

7.12 USING STORAGE ELEMENTS WITH CAD TOOLS

7.12.1 Including Storage Elements in Schematics

7.12.2 Using Latches and Flip-flops in VHDL Code

7.12.3 Using VHDL Sequential Statements for Storage Elements

7.13 USING REGISTERS AND COUNTERS WITH CAD TOOLS

7.13.1 Including Registers and Counters in Schematics

7.13.2 Registers and Counters in VHDL Code

7.13.3 Using VHDL Sequential Statements for Registers and Counters

7.14 DESIGN EXAMPLES

7.14.1 Bus Structure

7.14.2 Simple Processor

7.14.3 Reaction Timer

7.15 CONCLUDING REMARKS

7.16 PROBLEMS

7.17 REFERENCES

CHAPTER 8 SYNCHRONOUS SEQUENTIAL CIRCUITS

8.1 BASIC DESIGN STEPS

8.1.1 State Diagram

8.1.2 State Table

8.1.3 State Assignment

8.1.4 Choice of Flip-Flops and Derivation of Next-State and Output Expressions

8.1.5 Timing Diagram

8.1.6 Summary of Design Steps

8.2 STATE ASSIGNMENT PROBLEM

8.2.1 One-Hot Encoding

8.3 MEALY STATE MODEL

8.4 DESIGN OF FINITE STATE MACHINES USING CAD TOOLS

8.4.1 VHDL Code for Moore-type FSMs

8.4.2 Synthesis of VHDL Code

8.4.3 Simulating and Testing the Circuit

8.4.4 An Alternative Style of VHDL Code

8.4.5 Summary of Design Steps Using CAD Tools

8.4.6 Specifying the State Assignment in VHDL Code

8.4.7 Specification of Mealy FSMs Using VHDL

8.5 SERIAL ADDER EXAMPLE

8.5.1 Mealy-type FSM for Serial Adder

8.5.2 Moore-type FSM for Serial Adder

8.5.3 VHDL Code for the Serial Adder

8.6 STATE MINIMIZATION

8.6.1 Partitioning Minimization Procedure

8.6.2 Incompletely Specified FSMs

8.7 DESIGN OF A COUNTER USING THE SEQUENTIAL CIRCUIT APPROACH

8.7.1 State Diagram and State Table for a Modulo-8 Counter

8.7.2 State Assignment

8.7.3 Implementation Using D-type Flip-Flops

8.7.4 Implementation Using JK-type Flip-Flops

8.7.5 Example - A Different Counter

8.8 FSM AS AN ARBITER CIRCUIT

8.8.1 Implementation of the Arbiter Circuit

8.8.2 Minimizing the Output Delays for an FSM

8.8.3 Summary

8.9 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS

8.10 ALGORITHMIC STATE MACHINE (ASM) CHARTS

8.11 FORMAL MODEL FOR SEQUENTIAL CIRCUITS

8.12 CONCLUDING REMARKS

8.13 PROBLEMS

8.14 REFERENCES

CHAPTER 9 ASYNCHRONOUS SEQUENTIAL CIRCUITS

9.1 ASYNCHRONOUS BEHAVIOR

9.2 ANALYSIS OF ASYNCHRONOUS CIRCUITS

9.3 SYNTHESIS OF ASYNCHRONOUS CIRCUITS

9.4 STATE REDUCTION

9.5 STATE ASSIGNMENT

9.5.1 Transition Diagram

9.5.2 Exploiting Unspecified Next-State Entries

9.5.3 State Assignment Using Additional State Variables

9.5.4 One-Hot State Assignment

9.6 HAZARDS

9.6.1 Static Hazards

9.6.2 Dynamic Hazards

9.6.3 Significance of Hazards

9.7 A COMPLETE DESIGN EXAMPLE

9.7.1 The Vending Machine Controller

9.8 CONCLUDING REMARKS

9.9 PROBLEMS

9.10 REFERENCES

CHAPTER 10 DIGITAL SYSTEM DESIGN

10.1 BUILDING BLOCK CIRCUITS

10.1.1 Flip-flops and Registers with Enable Inputs

10.1.2 Shift Registers with Enable Inputs

10.1.3 Static Random Access Memory (SRAM)

10.1.4 SRAM Blocks in PLDs

10.2 DESIGN EXAMPLES

10.2.1 A Bit-Counting Circuit

10.2.2 ASM Chart Implied Timing Information

10.2.3 Shift-and-Add Multiplier

10.2.4 Divider

10.2.5 Arithmetic Mean

10.2.6 Sort Operation

10.3 CLOCK SYNCHRONIZATION

10.3.1 Clock Skew

10.3.2 Flip-flop Timing Parameters

10.3.3 Asynchronous Inputs to Flip-Flops

10.3.4 Switch Debouncing

10.4 SUMMARY

10.5 PROBLEMS

10.6 REFERENCES

CHAPTER 11 TESTING OF LOGIC CIRCUITS

11.1 FAULT MODEL

11.1.1 Stuck-at Model

11.1.2 Single and Multiple Faults

11.1.3 CMOS Circuits

11.2 COMPLEXITY OF A TEST SET

11.3 PATH SENSITIZING

11.3.1 Detection of a Specific Fault

11.4 CIRCUITS WITH TREE STRUCTURE

11.5 RANDOM TESTS

11.6 TESTING OF SEQUENTIAL CIRCUITS

11.6.1 Design for Testability

11.7 BUILT-IN SELF-TEST

11.7.1 Built-In Logic Block Observer

11.7.2 Signature Analysis

11.7.3 Boundary Scan

11.8 PRINTED CIRCUIT BOARDS

11.8.1 Testing of PCBs

11.8.2 Instrumentation

11.9 CONCLUDING REMARKS

11.10 PROBLEMS

11.11 REFERENCES

APPENDIX A VHDL REFERENCE

A.1 DOCUMENTATION IN VHDL CODE

A.2 DATA OBJECTS

A.2.1 Data Object Names

A.2.2 Data Object Values and Numbers

A.2.3 SIGNAL Data Objects

A.2.4 BIT and BIT_VECTOR Types

A.2.5 STD_LOGIC and STD_LOGIC_VECTOR Types

A.2.6 STD_ULOGIC Type

A.2.7 SIGNED and UNSIGNED Types

A.2.8 INTEGER Type

A.2.9 BOOLEAN Type

A.2.10 ENUMERATION Type

A.2.11 CONSTANT Data Objects

A.2.12 VARIABLE Data Objects

A.2.13 Type Conversion

A.2.14 Arrays

A.3 OPERATORS

A.4 VHDL DESIGN ENTITY

A.4.1 ENTITY Declaration

A.4.2 ARCHITECTURE

A.5 PACKAGE

A.6 USING SUBCIRCUITS

A.6.1 Declaring a COMPONENT in a Package

A.7 CONCURRENT ASSIGNMENT STATEMENTS

A.7.1 Simple Signal Assignment

A.7.2 Assigning Signal Values using OTHERS

A.7.3 Selected Signal Assignment

A.7.4 Conditional Signal Assignment

A.7.5 GENERATE Statement


A.8 DEFINING AN ENTITY WITH GENERICS

A.9 SEQUENTIAL ASSIGNMENT STATEMENTS

A.9.1 PROCESS Statement

A.9.2 IF Statement

A.9.3 CASE Statement

A.9.4 Loop Statements

A.9.5 Using a Process for a Combinational Circuit

A.9.6 Statement Ordering

A.9.7 Using a Variable in a PROCESS

A.10 SEQUENTIAL CIRCUITS

A.10.1 A Gated D Latch

A.10.2 D Flip-flop

A.10.3 Using a WAIT UNTIL Statement

A.10.4 A Flip-flop with Asynchronous Reset

A.10.5 Synchronous Reset

A.10.6 Instantiating a Flip-flop from a Library

A.10.7 Registers

A.10.8 Shift Registers

A.10.9 Counters

A.10.10 Using Subcircuits with GENERIC Parameters

A.10.11 A Moore-type Finite-state Machine

A.10.12 A Mealy-type Finite-state Machine

A.10.13 Manual State Assignment for a Finite-state Machine

A.11 COMMON ERRORS IN VHDL CODE

A.12 SUMMARY

A.13 REFERENCES

APPENDIX B TUTORIAL 1

B.1 INTRODUCTION

B.1.1 Getting Started

B.2 DESIGN ENTRY USING SCHEMATIC CAPTURE

B.2.1 Specifying the Project Name

B.2.2 Using the Graphic Editor

B.2.3 Synthesizing a Circuit from the Schematic

B.2.4 Performing Functional Simulation

B.2.5 Using the Message Processor to Locate and Fix Errors

B.3 DESIGN ENTRY USING VHDL

B.3.1 Specifying the Project Name

B.3.2 Using the Text Editor

B.3.3 Synthesizing a Circuit from the VHDL Code

B.3.4 Performing Functional Simulation

B.3.5 Using the Message Processor to Debug VHDL Code

B.4 DESIGN ENTRY USING TRUTH TABLES

B.4.1 Using the Waveform Editor

B.4.2 Create the Timing Diagram

B.4.3 Synthesizing a Circuit from the Waveforms

B.5 MIXING DESIGN ENTRY METHODS

B.5.1 Creating a Schematic that Includes a Truth Table

B.5.2 Synthesizing and Simulating a Circuit from the Schematic

B.5.3 Using the Hierarchy Display

B.5.4 Tutorial Summary

APPENDIX C TUTORIAL 2

C.1 IMPLEMENTING A CIRCUIT IN A MAX 7000 CPLD

C.1.1 Using the Compiler

C.1.2 Selecting a Chip

C.1.3 Viewing the Logic Synthesis Options

C.1.4 Examining the Implemented Circuit

C.1.5 Running the Timing Simulator

C.1.6 Using the Floorplan Editor

C.2 IMPLEMENTING A CIRCUIT IN A FLEX 10K FPGA

C.3 DOWNLOADING A CIRCUIT INTO A DEVICE

C.4 MAKING PIN ASSIGNMENTS

C.4.1 Assigning Signals to Pins in the Floorplan Editor

C.4.2 Making Pin Assignments Permanent

C.5 SUMMARY

APPENDIX D TUTORIAL 3

D.1 DESIGN USING HIERARCHICAL VHDL CODE

D.1.1 The Full-adder Subcircuit

D.1.2 The Ripple-carry Adder Code

D.1.3 Alternative Style of Code for the Ripple-carry Adder

D.1.4 Using the Timing Analyzer Module

D.2 USING AN LPM MODULE

D.3 DESIGN OF A SEQUENTIAL CIRCUIT

D.3.1 Using the Graphic Editor

D.3.2 Synthesizing a Circuit and Using the Timing Simulator

D.3.3 Using the Timing Analyzer

D.3.4 Using VHDL Code

D.4 DESIGN OF A FINITE STATE MACHINE

D.4.1 Implementation in a CPLD

D.4.2 Implementation in an FPGA

D.5 FINAL REMARKS

 

APPENDIX E COMMERCIAL DEVICES

E.1 Simple PLDs

E.1.1 The 22V10 PAL Device

E.2 Complex PLDs

E.2.1 Altera MAX 7000

E.3 Field-Programmable Gate Arrays

E.3.1 Altera FLEX 10K

E.3.2 Xilinx XC4000

E.4 Transistor-Transistor Logic

feedback form | permissions | international | locate your campus rep | request a review copy

digital solutions | publish with us | customer service | mhhe home


Copyright ©2001 The McGraw-Hill Companies.
Any use is subject to the Terms of Use and Privacy Policy.
McGraw-Hill Higher Education is one of the many fine businesses of the The McGraw-Hill Companies.